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nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 200 1 1 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. 16 mx64 bit two bank small outline sdram module based on 8 mx 16 , 4banks, 4 k refresh, 3.3v synchronous drams with spd features l 144 pin jedec standard, 8 byte small outline dual - in - line memory module l 16mx64 synchronous dram so dimm l inputs and outputs ar e lvttl (3.3v) compatible l 10 ohm resistors on dqs l single 3.3v 0.3v power supply l single pulsed ras interface l sdrams have four internal banks l fully synchronous to positive clock edge l data mask for byte read/write control l auto refresh (cb r) and self refresh l automatic and controlled precharge commands l programmable operation: - cas latency: 2, 3 - burst type: sequential or interleave - burst length: 1, 2, 4, 8, - operation: burst read and write or multiple burst read with single write l suspe nd mode and power down mode l 1 2 /9/2 addressing (row/column/bank) l 4096 refresh cycles distributed across 64ms l serial presence detect l gold contacts , jedec mo - 190 outline dimensions description nt128s64vh8c0gm is a 144 - pin synchronous dram small outline dual in - line memory module (so dimm) that is organized as a 16mx64 high - speed memory array. the so dimm uses eight 8 mx16 sdrams in 400mil tsop ii packages and achieves high - speed data transfer rates of up to 133 mhz by employing a prefetch / pipeline hybr id architecture that supports the jedec 1n rule while allowing very low burst power. all control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs. all inputs are sampled at the positi ve edge of the externally supplied clock (ck0 ,ck1 ). internal operating modes are defined by combinations of the ras , cas , we , s0 , s1 , dqmb, and cke0 ,cke1 si gnals. a command decoder initiates the necessary timings for each operation. a 1 4 bit address bus accepts address information in a row/column multiplexing arrangement. prior to any access operation, the cas latency, burst type, burst le ngth, and burst operation type must be programmed into the so dimm by address inputs a0 - a9 during the mode register set cycle. the so dimm uses serial presence detects implemented via a serial eeprom using the two pin iic protocol. the first 128 bytes of s erial pd data are used by the dimm manufacturer. the last 128 bytes are available to the customer. all nanya 144 - pin so dimms provide a high performance, flexible 8 - byte interface in a 2.66" long space - saving footprint. ordering information speed part number mhz. cl t rcd t rp organization leads power 143mhz 3 3 3 nt128s64vh8c0gm - 7k 133mhz 2 2 2 133mhz 3 3 3 nt128s64vh8c0gm - 75b 100mhz 2 2 2 125mhz 3 3 3 nt128s64vh8c0gm - 8b 100mhz 2 2 2 16mx64 gold 3.3v * cl = cas latency
nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 200 1 2 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. pi n description ck0 , ck1 clock inputs dq0 - dq63 data input/output cke0 , cke1 clock enable dqmb0 - dqmb7 data mask ras row address strobe v dd power (3.3v) cas column address strobe v ss ground we wr ite enable nc no connect s0 , s1 chip selects scl serial presence detect clock input a0 - a9, a11 address inputs sda serial presence detect data input/output a10 / ap address input/autoprecharge du don ? t use ba0, b a1 sdram bank address pinout pin front pin back pin front pin back pin front pin back 1 v ss 2 v ss 51 dq14 52 dq46 95 dq21 96 dq53 3 dq0 4 dq32 53 dq15 54 dq47 97 dq22 98 dq54 5 dq1 6 dq33 55 v ss 56 v ss 99 dq23 100 dq55 7 dq2 8 dq34 57 nc 58 nc 101 v dd 102 v dd 9 dq3 10 dq35 59 nc 60 nc 103 a6 104 a7 11 v dd 12 v dd 105 a8 106 ba0 13 dq 4 14 dq 36 107 v ss 108 v ss 15 dq 5 16 dq 37 voltage key 109 a9 110 ba1 17 dq 6 18 dq 38 61 ck0 62 ck e0 111 a10/ ap 112 a11 19 dq 7 20 dq 39 63 v dd 64 v dd 113 v dd 114 v dd 21 v ss 22 v ss 65 ras 66 cas 115 dqmb 2 116 dqmb 6 23 dqmb0 24 dqmb 4 67 we 68 cke1 117 dqmb 3 118 dqmb 7 25 dqmb1 26 dqmb 5 69 s0 70 nc 119 v ss 120 v ss 27 v dd 28 v dd 71 s1 72 nc 121 dq 24 122 dq 56 29 a0 30 a3 73 d u 74 ck1 123 dq 25 124 dq 57 31 a1 32 a4 75 v ss 76 v ss 125 dq 26 126 dq 58 33 a2 34 a5 77 nc 78 nc 127 dq 27 128 dq 59 35 v ss 36 v ss 79 nc 80 nc 129 v dd 130 v dd 37 dq 8 38 dq40 81 v dd 82 v dd 131 dq 28 132 dq 60 39 dq9 40 dq41 83 dq16 84 dq48 133 dq 29 134 dq 61 41 dq10 42 dq42 85 dq17 86 dq49 135 dq 30 136 dq 62 43 dq11 44 dq43 87 dq18 88 dq50 137 dq 31 138 dq 63 45 v dd 46 v dd 89 dq19 90 dq51 139 v ss 140 v ss 47 dq12 48 dq44 91 v ss 92 v ss 141 sda 142 scl 49 dq13 50 dq45 93 dq20 94 dq52 143 v dd 144 v dd note: all pin assignments are consistent for all 8 - byte versions.
nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 200 1 3 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. sdram dimm block diagram ( 2 bank, 8 mx 16 sdrams) s0 dqmb0 ldqm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d0 dqmb4 ldqm dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d2 dqmb1 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmb5 udqm dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ras cas cke0 we a0-a11 ba0 ba1 sdrams d0-d7 sdrams d0-d7 sdrams d0-d3 sdrams d0-d7 sdrams d0-d7 sdrams d0-d7 sdrams d0-d7 spd a0 a1 a2 scl v dd v ss d0 - d7 d0 - d7 sda ck0 / ck1 ck1 10pf dqmb2 ldqm dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d1 dqmb6 ldqm dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d3 dqmb3 udqm dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmb7 udqm dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 10ohm d0 / d4 d1 / d5 d2 / d6 d3 / d7 dqn every dq pin of sdram ldqm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d4 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ldqm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d6 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ldqm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d5 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ldqm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs d7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 s1 cke1 sdrams d4-d7
nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 200 1 4 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. input/output functional description symbol type signal pol arity function ck0 , ck1 input pulse positive edge the system clock inputs. all of the sdram inputs are sampled on the rising edge of their associated clock. cke0 , cke1 input level active high activates the sdram ck0 and ck1 signals when high and deactiv ates them when low. by deactivating the clocks, cke0 low initiates the power down mode, suspend mode, or the self - refresh mode. s0 , s1 input pulse active low enables the associated sdram command decoder when low an d disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas , we input pulse active low when sampled at the p ositive rising edge of the clock, ras , cas , we define the operation to be executed by the sdram. ba0, ba1 input level - selects which sdram bank is to be active. a0 ? a1 1 a10/ap input level - du ring a bank activate command cycle, a0 - a1 1 defines the row address (ra0 - ra1 1 ) when sampled at the rising clock edge. during a read or write command cycle, a0 - a 9 defines the column address (ca0 - ca 9 ) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0/ba1 define the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge com mand cycle, ap is used in conjunction with ba0/ba1 to control which bank(s) to precharge. if ap is high all 4 banks will be precharged regardless of the state of ba0/ba1. if ap is low, then ba0/ba1 are used to define which bank to pre - charge. dq0 - dq63 i nput /output level - data and check bit input/output pins operate in the same manner as on conventional drams. dqmb0 - dqmb7 input pulse active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if dqm is hi gh. sda input /output level - serial data. bi - directional signal used to transfer data into and out of the serial presence detect eeprom. since the sda signal is open drain/open collector at the eeprom, a pull - up resistor is required on the system board. scl input pulse - serial clock. used to clock all serial presence detect data into and out of the eeprom. since the scl signal is inactive in the ?high? state, a pull - up resistor is recommended on the system board. v dd , v ss supply power and ground for the module.
nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 200 1 5 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. absolute maximum ratings symbol parameter rating units notes v dd power supply voltage - 0.3 to +4.6 v in input voltage - 0.3 to v dd +0.3 v out output voltage - 0.3 to v dd +0.3 v 1 t a operating temperature (ambient) 0 to +70 c 1 t s tg storage temperature - 55 to +125 c 1 p d power dissipation 3.5 w 1 i out short circuit output current 50 ma 1 1.1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended dc operating conditions (t a =0 to 7 0 c ) rating symbol parameter min. typ. max. units notes v dd power voltage 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 - v dd + 0.3 v 1,2 v il input low voltage - 0.3 - 0.8 v 1,3 v oh out put high voltage 2.4 - - v v ol out put low voltage - - 0.4 v i il input leakage current - 10 - 10 a 1. all voltages referenced to v ss . 2. v ih (max) = v dd / v dd q + 1.2v for pulse width 5ns 3. v il (min) = v ss / v ssq - 1.2v for pulse width 5ns . capacitance (t a =2 5 c , f =1mhz, v dd =3.3 0.3v) symbol parameter max. un it c i1 input capacitance (a0 - a9, a10/ap, a11, a12, ba0, ba1, ras , cas , we ) 58 c i2 input capacitance (cke0 ,cke1 ) 28 c i3 input capacitance ( s0 , s1 ) 28 c i4 input capacitance (ck0 ,ck1 ) 32 c i5 input capacitance (dqmb0 - dqmb7) 14 c i6 input capacitance (scl) 13 c io1 input/output capacitance (dq0 - dq63) 17 c io2 input/output capacitance (sda) 15 pf dc output load circuit v oh (dc) = 2.4v,i oh = -2ma v ol (dc) = 0.4v,i ol = -2ma 3.3 v 1200 ohms 870 ohms 50 pf output
nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 200 1 6 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. operating, standby, and refresh currents (t a =0 to 70 c , v dd =3.3 0.3v) speed parameter symbol test condition - 7 k - 75 b - 8 b unit note operating current i cc1 1 bank operation , t rc = t rc (mim), t ck = min active - precharge command cycling withou t burst operation 720 680 640 ma 1, 2 i cc2p cke v il (max), t ck = min, s0 , s1 = v ih (min) 16 ma precharge standby current in power - down mode i cc2ps cke v il (max), t ck = oo , s0 , s1 = v ih (min) 16 ma i cc2n cke0 3 v ih (min), t ck = min s0 , s1 = v ih (min) 400 360 280 ma 3 precharge standby current in non power - down mode i cc2ns cke 3 v ih (min), t ck = oo, s0 , s1 = v ih (min) 72 72 72 ma 4 i cc3p cke v il (max), t ck = min . s0 , s1 = v ih (min) , (power down mode) 72 72 72 ma 5 no operating current ( active state : 4 bank) i cc3n cke0 3 v ih (min), t ck = min s0 = v ih (min) 400 400 320 ma 3 operating current ( burst mode ) i cc4 t ck =min , read/ write command cycling, multiple banks active, gapless data, bl=4 810 720 540 ma 2, 6 auto(cbr) refresh current i cc5 t ck =min , cbr command cycling 960 960 860 ma self refresh current i cc6 cke0 0.2v 16 ma serial pd device standby current i sb v in = gnd or v dd 30 m a 7 1. these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t r c . input signals are changed up to three times during t rc (min). 2. the specified values are obtained with the output open. 3. input signals are changed once during three clock cycles. 4. input signals are stable. 5. active standby current will be higher if clock suspend is entered during a burst read cycle (add 1ma per dq). 6. input signals are changed once during t ck (min) . 7. v dd =3.3v
nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 200 1 7 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac characteristics (t a =0 to 70 c , v dd =3.3 0.3v) 1. an initial pause of 200 , with dqmb0 - 7 and cke hel d high, is required after power - up. a precharge all banks command must be given followed by a minimum of eight auto (cbr) refresh cycles before or after the mode register set operation. 2. the transition time is measured between v ih and v il (or between v ih and v il ). 3. in addition to meeting the transition rate specification, the c l k and cke signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. ac timing tests have v il =0.8v and v ih = 2.0 v with the timing referenced to the 1.40v cross over point. 5. ac measurements assume t t =1.2 ns. ac output load circuits clock input output t hold t setup t ckl t ckh t t v ih v il 1.4v 1.4v t ac t lz toh 1.4v output zo = 50 ohm 50 pf ac output load circuit
nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 200 1 8 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac timing parameters clock and clock enable parameters - 7 k - 75 b - 8 b symbol parameter min. ma x. min. max. min. max. unit note tck3 clock cycle time, cas latency = 3 7 1000 7.5 1000 8 1000 ns tck2 clock cycle time, cas latency = 2 7.5 1000 10 1000 1 0 1000 ns tac3(b) clock access time, cas late ncy = 3 - 5.4 - 5.4 - 6 ns 1 tac2(b) clock access time, cas latency = 2 - 5.4 - 6 - 6 ns 1 tckh clock high pulse width 2.5 - 2.5 - 3 - ns 2 tckl clock low pulse width 2.5 - 2.5 - 3 - ns 2 tces clock enable set - up time 1.5 - 1.5 - 2 - ns tceh clock enable hold time 0.8 - 0.8 - 1 - ns tsb power down mode entry time 0 7.5 0 7.5 0 12 ns tt transition time (rise and fall) 0.5 10 0.5 10 0.5 10 ns 1. access time is measured at 1.4v. in ac characteristics section, see notes. 2. t ckh is the pulse width of clk measured from the positive edge to the negative edge referenced to v ih (min). t ckl is the pulse width of clk measured from the negative edge to the positive edge referenced to v il (max). common parameters - 7 k - 75 b - 8 b symbol parameter min. max. min. max. min. max. unit note tcs command setup time 1.5 - 1.5 - 2 - ns tch command hold time 0.8 - 0.8 - 1 - ns tas address and bank select set - up time 1.5 - 1.5 - 2 - ns tah address and bank select hold time 0.8 - 0.8 - 1 - ns trcd ras to cas delay 20 - 20 - 20 - ns 1 trc bank cycle time 6 0 - 6 7.5 - 70 - ns 1 tr f c auto refresh to active/auto refresh 60 - 67.5 - 70 - tras active command period 45 100k 45 100k 50 100k ns 1 trp precharge time 20 - 20 - 20 - ns 1 trrd bank to bank delay time 15 - 15 - 20 - ns 1 tccd cas to cas delay time 1 - 1 - 1 - clk 1. these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). mode register set cycle - 7 k - 75 b - 8 b symbol parameter min. max. min. max. min. max. unit note trsc mode register s et cycle time 2 - 2 - 2 - clk 1 1. these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole numbe r).
nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 200 1 9 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. read cycle - 7 k - 75 b - 8 b symbol parameter min. max. min. max. min. max. unit note - - - - 2.5 - ns toh data out hold time 2.7 - 2.7 - 3 - ns tlz data out to low impedance time 0 - 0 - 0 - ns thz3 data out to high impedance time 3 5. 4 3 5.4 3 6 ns 1 tdqz dqm data out disable latency 2 - 2 - 2 - clk 1. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. refresh cycle - 7 k - 75 b - 8 b symbol parameter min. max. m in. max. min. max. unit note tref refresh period - 64 - 64 - 64 ms tsrex self refresh exit time 10 - 10 - 10 - ns write cycle - 7 k - 75 b - 8 b symbol parameter min. max. min. max. min. max. unit note tds data in set - up time 1.5 - 1.5 - 2 - ns tdh data in hold time 0.8 - 0.8 - 1 - ns tdpl data input to precharge 15 - 15 - 15 - ns tdal3 data in to active delay cas latency = 3 5 - 5 - 5 - clk tdal2 data in to active delay cas latency = 2 5 - - - - - clk tdqw dqm write mask latency 0 - 0 - 0 - ns
nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 200 1 10 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. serial presence detect -- part 1 of 2 32 mx64 sdram so dimm based on 8 mx 16 , 4banks, 4 k refresh, 3.3 v sdrams with sp d spd entry value serial pd data entry (hexadecimal) byte description - 7k - 75b - 8b - 7k - 75 - 8b note 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type s dram 04 3 number of row addresses on assembly 1 2 0c 4 number of column addresses on assem bly 9 0 9 5 number of dimm bank 2 0 2 6 data width of assembly x64 40 7 data width of assembly (cont?) x64 00 8 voltage interface level of this assembly lvttl 01 9 sdram device cycle time at cl= 3 7ns 7.5ns 8ns 70 75 80 10 sdram device access time from clock at cl= 3 5.4ns 5.4ns 6 ns 54 54 60 11 dimm configuration type non - parity 00 12 refresh rate/type 15.625 s / sr 8 0 13 primary sdram width x16 10 14 error checking sdram device width n/a 00 15 sdram device attributes : min imum c loc k dela y, random col umn access 1 clock 01 16 sdram device attributes: burst length supported 1, 2,4,8 0 f 17 sdram device attributes: number of device banks 4 04 18 sdram device attributes: cas latency 2, 3 2 , 3 2 , 3 0 6 0 6 0 6 19 sdram dev ice attributes: cs latency 0 01 20 sdram device attributes: we latency 0 0 1 21 sdram module attributes unbuffered 00 22 sdram device attributes: general wr - 1/rd burst, precharge all, auto - precharge, v dd +/ - 10% 0e 23 minimum clock cycle at cl=2 7.5ns 10ns 10ns 75 a0 a0 24 maximum data access time from clock at cl=2 5.4ns 6ns 6ns 54 60 60 25 minimum clock cycle time at cl=1 n/a 00 26 maximum data access time from clock at cl=1 n/a 00 27 minimum row prec harge time ( t r p ) 15 ns 20ns 20ns 0f 14 14 28 minimum row active to row active delay ( t r rd ) 15ns 15ns 20 ns 0f 0f 14 29 minimum ras to cas delay ( t r cd ) 15 ns 20ns 20ns 0f 14 14 30 minimum ras pulse width ( t ras ) 45ns 45ns 50ns 2d 2d 32 31 module bank de nsity 64 mb 1 0 32 address and command setup time before clock 1 . 5 ns 1 . 5 ns 2ns 15 15 20 33 address and command hold time after clock 0. 8 ns 0. 8 ns 1ns 08 08 10 34 data input setup time before clock 1 . 5 ns 1 . 5 ns 2ns 15 15 20 35 data input hold time after clock 0. 8 ns 0. 8 ns 1ns 08 08 10 36 - 61 reserved undefined 00 62 spd revision 1.2 1.2 1.2 12 12 12 63 checksum for bytes 0 - 62 e1 27 6e
nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 200 1 11 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. serial presence detect -- part 2 of 2 32 mx64 sdram so dimm based on 8 mx 16 , 4banks, 4 k refresh, 3.3 v sdram s with sp d spd entry value serial pd data entry (hexadecimal) byte description - 7k - 75b - 8b - 7k - 75 b - 8b note 64 - 71 manufacturer?s jeded id code 0 b hex. bank 3 7f7f7f0b 00000000 3 72 module manufacturing location n/a 00 73 - 90 module part number n/a n/a n/a 00 00 00 91 - 92 module revision code n/a 00 93 - 94 module manufacturing data year/week code yy/ww 1,2 95 - 98 module serial number serial number 00 99 - 125 reserved undefined 00 126 modules supports this clock frequency 100mhz 64 127 attribu tes for clock frequency defined in byte 126 ck0, ck1, ck2,ck3, cl3, cl2 concurrent ap ff 128 - 255 open for customer use undefined 00 1. yy= binary coded decimal year code, 0 - 99(decimal) , 00 - 63(hex) 2. ww= binary coded decimal year code, 01 - 52(decimal) , 01 - 34( hex) 3. nanya 11decimal (bank four) 0000 1011 binary 0b hex.
nt 128s64vh8c0gm 128mb : 16 m x 64 sdram sodimm preliminary july / 2001 12 ? nan ya technology cor p. nanya technology cor p . reserves the right to change products and specifications without notice. package dimensions note : all dimension s are typical unless otherwise stated. 2.661 2.505 0.157+/-0.004 0.059+/- 0.004 front side 0.039+/- 0.004 detail a 0.100 0.031 detail b 0.024 0.010 max 143 1 59 61 detail a detail b unit : inch e s 0.157 0.787 1.250 0.236 0.130 0.913 0.181 0.098 1.291 0.150 max 2 60 62 144 (2x) q 0.071

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